Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
We are looking for someone who brings deep expertise in analog and mixed-signal layout, along with the leadership to improve execution at scale through AI-enabled productivity, automation, and methodology innovation. At Synopsys, you will work on SerDes analog layout in advanced nodes, lead execution across complex programs, and help modernize how layout engineering gets done.
Key Responsibilities:
- Lead delivery of SerDes analog layout programs in advanced process nodes, owning execution quality, schedule predictability, and technical risk management
- Drive layout methodology improvements across floorplanning, matching, shielding, ESD integration, and physical verification workflows
- Collaborate regularly with design engineers, ESD teams, reliability engineers, CAD teams, and program managers to align layout execution with design intent and program milestones
- Deploy automation, scripting, dashboards, and AI-assisted workflows to reduce manual effort, improve consistency, and scale engineering productivity
- Mentor layout engineers on advanced techniques, design tradeoffs, and execution rigor, raising the technical bar across the team
- Influence cross-functional decisions on layout planning, resource allocation, tool adoption, and process improvements
Impact:
- Deliver high-speed analog layouts that meet performance, reliability, and manufacturability requirements in advanced nodes
- Reduce layout cycle time and rework through better automation, clearer handoffs, and smarter use of verification tools and AI-enabled workflows
- Strengthen cross-team collaboration so design, layout, ESD, and CAD work as one integrated execution engine, not siloed functions
- Build reusable layout methodologies and automation frameworks that scale across programs and geographies
- Elevate engineering capability through mentorship, technical leadership, and clear execution standards that make the team stronger over time
- Contribute to successful tapeouts of industry-leading SerDes IP that powers next-generation semiconductor products
Requirements:
- Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related field
- 12+ years experience in analog or custom layout for high-speed analog and mixed-signal designs
- Deep expertise in layout implementation and related methodology in advanced process nodes
- Proven track record working across design, layout, ESD, CAD, and program teams to deliver complex layouts on schedule
- Experience improving engineering productivity through automation, methodology enhancement, dashboards, or workflow optimization
- This role requires experience in leading teams, planning execution, mentoring engineers, owning delivery outcomes, technical leadership, deep problem-solving ability, and cross-team methodology influence; experience or strong interest in applying AI and automation to layout workflows is a plus