Description
You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs.
Job Description
You will independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
Your responsibilities include:
- Executing synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.
- Performing block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
- Collaborating with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
- Utilizing and optimizing Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
- Developing and maintaining automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
- Contributing to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.
Requirements
- Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
- 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
- Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification.
- Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
- Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
- Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
- Exposure to high-frequency design and low-power design methodologies.
Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
This listing is enriched and indexed by YubHub. To apply, use the employer's original posting:
https://careers.synopsys.com/job/bengaluru/senior-staff-soc-engineer-physical-design/44408/97746861920