Senior Physical Design Verification Layout Engineer

We are looking for a best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team. As a Senior Physical Design Verification Layout Engineer, you will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds. You will also run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards. Additionally, you will perform physical layout implementation, planning, and optimization, contributing to the development of our groundbreaking chips.

Requirements:

• B.SC./ M.SC. in Electrical Engineering
• At least 5+ years of hands-on layout experience
• Strong background in Physical Verification methodology, including ERC, LVS, and DRC
• In-depth knowledge of advanced silicon process technologies
• Familiarity with physical build EDA tools, including Synopsys and Cadence
• Great teammate who thrives in a collaborative environment
• AI tools orientation or alternatively a desire to learn

Nice to Have:

• Experience in Linux environments
• TCL, Python, shell scripting abilities
• Experience with data collection and analysis
• Understanding of the chip and die verification process