Description
Design Verification, Forward Deployed Engineering
Compensation
We offer a competitive salary range of $162K – $302K, including generous equity, performance-related bonus(es) for eligible employees, and the following benefits:
- Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
- Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
- 401(k) retirement plan with employer match
- Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
- Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
- 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
- Mental health and wellness support
- Employer-paid basic life and disability coverage
- Annual learning and development stipend to fuel your professional growth
- Daily meals in our offices, and meal delivery credits as eligible
- Relocation support for eligible employees
- Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.
About the Team
OpenAI's Forward Deployed Engineering team partners with leading semiconductor companies to deploy production-grade AI systems across the entire chip design lifecycle: design, verification, and physical design. We operate at the intersection of customer delivery and core platform development, embedding deeply with customers to translate frontier model capabilities into systems that materially reduce design cycles, improve verification quality, and accelerate innovation.
About the Role
We are seeking an experienced Design Verification Engineer to join our semiconductor-focused Forward Deployed Engineering team. This is an IC role that will begin with a strong emphasis on design verification expertise, evaluation curation, and technical leverage across deployments, with the expectation that the person will grow into a broader Forward Deployed Engineering role over time.
In the near term, you will serve as a senior technical SME for verification workflows: helping FDEs, Product, and Research teams understand how DV work is done in practice, pressure-testing AI-assisted verification ideas against real engineering workflows, and raising the quality of our solutions through deep domain judgment. You will help the broader team build fluency in verification methodology, tooling, and trade-offs.
Over time, we expect this role to expand beyond SME support into broader FDE ownership: partnering directly with customers, shaping deployment strategy, building and iterating production-grade AI systems, driving technical workstreams, and helping turn high-touch semiconductor deployments into repeatable solutions.
This is a strong fit for someone who brings deep design verification expertise today and is excited to grow into a customer-facing, systems-building, delivery-oriented FDE role.
Minimum Qualifications
- BS/MS in EE, CE, CS, or equivalent with 5+ years of experience in design verification for complex IP, subsystem, or SoC programs
- Demonstrated success verifying complex hardware systems in industry-standard flows, with deep familiarity in block-, subsystem-, and/or top-level verification methodologies
- Strong hands-on expertise in SystemVerilog, UVM, and common simulation/debug tools such as VCS, Questa, Verdi, or equivalent
- Strong understanding of constrained-random verification, directed testing, scoreboards, checkers, monitors, stimulus generation, regression infrastructure, and coverage analysis
- Strong knowledge of computer architecture, RTL/microarchitecture, memory systems, coherency, interconnects, and verification methodology
- Experience defining verification plans, triaging bugs, and driving debug and root-cause analysis in close partnership with design teams
- Strong scripting and automation skills in Python or similar; experience building verification tooling, harnesses, or workflow automation is a plus
- Comfortable operating as a consultative expert who can shape technical direction, evaluate solution quality, and raise the bar across multiple deployments
- Excited to grow beyond domain SME responsibilities into a broader Forward Deployed Engineering role, including hands-on solution building, customer-facing delivery, and ownership of deployment outcomes
Preferred Qualifications
- Experience across multiple semiconductor companies, design environments, or tool stacks, with a point of view shaped by different verification cultures and methodologies
- Familiarity with adjacent domains such as RTL design, formal verification, emulation, performance analysis, or physical design
- Experience applying AI/LLM systems to semiconductor workflows
- Experience creating reusable evals, methodology assets, or technical playbooks
- Prior experience in customer-facing, consultative, field engineering, solutions engineering, or technical delivery roles