Description
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
Job Description
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
You Are:
You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.
Responsibilities
Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.
Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.
Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.
Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.
Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.
Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.
Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.
4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.
Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.
Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.
Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.
Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.
Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).
Exposure to quality processes in IP design and verification is an advantage.
Prior experience as a technical lead or mentor is highly desirable.
Who We Are Looking For
Innovative thinker with a solutions-oriented mindset and a passion for technology.
Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.
Natural leader with mentoring abilities, fostering inclusion and diversity within the team.
Detail-oriented professional with strong analytical and problem-solving skills.
Self-motivated, adaptable, and eager to drive technical excellence and process improvements.
Committed to continuous learning and staying ahead of industry trends.
The Team You’ll Be A Part Of
You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.