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SystemVerilog jobs
14 employers are hiring for 220 live roles that ask for SystemVerilog, with Bengaluru, Santa Clara and Hyderabad the busiest cities, and where pay is shown, the median is $184k. Browse them all, filter by location or remote, or set a free alert for new ones.
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Live roles
220
Employers
14
Median salary
$184k
Locations
61
Filters
Work type
Experience
220 roles
Latest roles
220 jobs · page 1 of 5
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4 Nov 2026 - 4 Nov 2026
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4 Nov 2026 - 4 Nov 2026
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$98,600 - $133,400 3 Nov 2026 -
ASIC front-end verification engineerOn-site mid3 Nov 2026 - ASIC Verification EngineerOn-site senior3 Nov 2026
- $107,800 - $157,400 2 Nov 2026
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Hourly Salary USD 35.00 - 41.00 1 Nov 2026 - Senior ASIC Design Verification Engineer - SlingshotHybrid seniorUSD 147,000 - 279,000 in Colorado // 140… 1 Nov 2026
- ASIC Design Verification Engineer - SlingshotHybrid seniorAnnual Salary USD 115,000 - 218,000 in C… 1 Nov 2026
- $125,700 - $203,100 1 Nov 2026
- $167,700 - $245,200 1 Nov 2026
- $35.00 - $41.00 per hour 1 Nov 2026
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1 Nov 2026 - ASIC Verification EngineerHybrid seniorAnnual Salary USD 120,000 - 243,000 31 Oct 2026
- Senior Methodologist for AIML Enhanced Design/VerificationOn-site seniorAnnual Salary USD 174,000 - 352,500 31 Oct 2026
- ASIC Design Verification EngineerOn-site senior31 Oct 2026
- 31 Oct 2026
- 31 Oct 2026
- 31 Oct 2026
- 31 Oct 2026
- 31 Oct 2026
- 31 Oct 2026
- 31 Oct 2026
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196,000 USD – 310,500 USD 31 Oct 2026 - 168,000 USD – 264,500 USD for Level 4 31 Oct 2026
- $122000-$183000 30 Oct 2026
- 30 Oct 2026
- $138000-$208000 30 Oct 2026
- ASIC Digital Verification, Sr Staff EngineerOn-site senior29 Oct 2026
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29 Oct 2026 - 29 Oct 2026
- $136,000 - $218,500 for Level 3 and $168… 29 Oct 2026
- VLSI Design Verification InternHybrid entry$35.00 - $41.00 per hour 29 Oct 2026
- ASIC / FPGA Design Verification Engineer – (Lead or Senior)On-site senior$146,200 - $197,800 29 Oct 2026
- ASIC Verification Engineering InternHybrid entryHourly Salary USD 35.00 - 41.00 29 Oct 2026
- Annual Salary USD 105,500 - 243,000 29 Oct 2026
- Annual Salary USD 124,000 - 251,000 29 Oct 2026
- Principal ASIC Verification EngineerHybrid seniorAnnual Salary USD 181,000 - 367,000 28 Oct 2026
- Senior Principal ASIC Design EngineerHybrid seniorAnnual Salary USD 181,000 - 367,000 28 Oct 2026
- Annual Salary USD 120,000 - 243,000 28 Oct 2026
- Hourly Salary USD 35.00 - 41.00 in Calif… 28 Oct 2026
- 27 Oct 2026
- $160000-$240000 27 Oct 2026
- 27 Oct 2026
- SoC Performance Verification R&D EngineerOn-site senior27 Oct 2026
- ASIC Engineering Digital Design Leader (Digital design, FSM, CPU sub-systems, complex SOCs)On-site senior27 Oct 2026
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26 Oct 2026 - 26 Oct 2026
SystemVerilog skills: Salary range
From 156 disclosed salaries.
Low
$70k
Median
$184k
High
$367k
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Top SystemVerilog roles
- ASIC Verification Engineer 13
- Senior Verification Engineer 9
- Sr. Staff Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR) 5
- Senior ASIC Verification Engineer 5
- Verification Engineer 4
- ASIC Engineer 3
- Applications Engineering, Sr Engineer 3
- Senior FPGA Verification Engineer 3
- Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) 3
- Principal Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR) 3
SystemVerilog jobs by city
- Bengaluru 54
- Santa Clara 24
- Hyderabad 17
- Sunnyvale 12
- Austin 10
- Bristol 6
- Shanghai 5
- Roseville 4
- Mississauga 4
- Dublin 4
- Costa Mesa 4
- San Francisco 3