Description
We are seeking an ASIC Verification Engineer to join our team in Bengaluru, Karnataka, India. As an ASIC Verification Engineer, you will develop and enhance ASIC verification environments using the latest methodologies such as UVM. You will architect and build block-level, subsystem, and full-chip verification environments using SystemVerilog and UVM. You will define, design, and execute verification suites and test cases for complex ASICs using front-end simulators such as VCS and NC. You will independently verify large ASIC blocks and drive tape-out readiness through code coverage, functional coverage, and gate-level simulation analysis. You will collaborate with logic designers to debug and resolve design issues, and work with software teams during bring-up and validation. You will develop Perl, Python, and/or Shell scripts to improve verification infrastructure, automation, and methodology.
To be successful in this role, you will need to have a Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE). You will need 5+ years of experience in ASIC Verification, strong experience with SystemVerilog for ASIC verification, experience with constrained-random verification techniques, hands-on experience with industry-standard verification methodologies such as OVM, VMM, or UVM, and proficiency in Perl, Tcl, Python, or Shell scripting (Perl/Tcl preferred).
We offer a comprehensive suite of benefits that supports the physical, financial, and emotional wellbeing of our team members and their loved ones. We invest in your career and provide specific programs to help you reach your career goals. We are an unconditionally inclusive organization that celebrates individual uniqueness.