Description
Join the SiliconOne team at Cisco in Belgrade, Serbia, specializing in ASIC functional verification for Cisco Silicon One chips used in major data centers worldwide.
Your role involves functional verification using SystemVerilog/UVM, collaborating with global teams, design and block owners, and contributing to various development stages.
Key responsibilities include:
- Implementing DV infrastructure for block, cluster, and TOP-level environments
- Maintaining and enhancing existing DV environments
- Ensuring complete verification coverage through code and functional coverage implementation and review
- Working closely with architects and designers to ensure verification completeness
- Supporting tests done with emulation
- Preparing for post-silicon-validation
Requirements:
- 5+ years of experience in digital logic design verification
- Advanced knowledge of SystemVerilog and UVM
- Advanced debug skills pre-silicon and in-lab
Preferred qualifications:
- Scripting abilities
- System integration knowledge (AMBA, PCIe, SPI, I2C, JTAG, CPU)
- Basic software knowledge (driver level)
- Basic design knowledge