Description
You will be a Senior Applications Engineer (Functional Verification) at Synopsys, working with customers to drive deployments of VCS/Verdi simulation/debug technology.
Your main responsibilities will include:
- Driving customer deployments of VCS/Verdi simulation/debug technology, working closely with product teams and R&D to ensure successful adoption and integration.
- Diagnosing and troubleshooting complex technical issues in verification flows, utilizing good product knowledge and analytical skills.
- Collaborating with global domain experts to gather requirements and contribute to the development of a robust product roadmap.
- Driving competitive engagements by demonstrating Synopsys VCS/Verdi advantages and supporting customers in benchmarking scenarios.
- Interfacing directly with customers, product validation, and R&D teams to propose solutions and suggest improvements in implementation and validation processes.
- Developing and optimizing scripts (Perl, TCL, Shell, Make, Python) to enhance productivity and workflow automation.
The impact you will have includes:
- Enabling customers to accelerate their verification cycles and achieve first-pass silicon success through expert support and deployment of VCS simulation technology.
- Driving innovation in verification methodologies by integrating advanced features and AI-driven productivity tools.
- Enhancing Synopsys’ product offerings by providing actionable feedback from customer engagements and competitive benchmarking.
- Facilitating seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.
- Supporting the continuous improvement of VCS/Verdi and related technologies through proactive problem-solving and technical expertise.
- Contributing to the growth of Synopsys’ leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.
To be successful in this role, you will need:
- A Bachelor’s degree in Electronics with 4+ years or Master’s degree in Electronics with 2+ years of experience.
- Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.
- Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.
- Proven experience in debugging simulation mismatches and verification flows.
- Advanced scripting skills (Perl, TCL, Make, Shell, Python) and working knowledge of UNIX environments.
- Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.
- Exposure to GenAI technologies is a plus.
You will also need excellent written and oral communication skills, be a collaborative team player with a proactive and innovative mindset, detail-oriented and organized, able to manage multiple tasks and priorities, motivated self-starter with strong problem-solving abilities, and adaptable and open to travel.