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SystemVerilog jobs
14 employers are hiring for 220 live roles that ask for SystemVerilog, with Bengaluru, Santa Clara and Hyderabad the busiest cities, and where pay is shown, the median is $184k. Browse them all, filter by location or remote, or set a free alert for new ones.
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Live roles
220
Employers
14
Median salary
$184k
Locations
61
Filters
Work type
Experience
220 roles
Latest roles
220 jobs · page 2 of 5
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$155,000 to $222,600 26 Oct 2026 -
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125,000 CAD - 175,000 CAD for Level 3, a… 26 Oct 2026 -
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$208000-$311000 26 Oct 2026 -
$69,550 - $125,725 26 Oct 2026 -
ASIC Verification EngineerOn-site senior26 Oct 2026 -
Senior Design Verification EngineerHybrid seniorAnnual Salary USD 153,500 - 310,500 26 Oct 2026 -
$192,400 to $275,800 26 Oct 2026 -
Design Verification ManagerOn-site seniorAnnual Salary USD 174,000 - 352,500 25 Oct 2026 -
25 Oct 2026 -
25 Oct 2026 -
Senior ASIC Design Verification Engineer - SlingshotHybrid seniorAnnual Salary USD 147,000 - 279,000 in C… 25 Oct 2026 -
$147,000 - $279,000 per year in Colorado… 25 Oct 2026 -
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€51,000-€77,000 23 Oct 2026 -
$129,000-$193,000 23 Oct 2026 -
$191000-$286000 22 Oct 2026 -
136,000 USD - 218,500 USD for Level 3, a… 21 Oct 2026 -
20 Oct 2026 -
29 CAD - 53 CAD 20 Oct 2026 -
$165,000-$218,000 USD 17 Oct 2026 -
$191,000-$253,000 USD 17 Oct 2026 -
$191,000-$253,000 USD 17 Oct 2026 -
$106000-$160000 17 Oct 2026 -
16 Oct 2026 -
Sr Staff High-Speed Interface Verification EngineerOn-site senior16 Oct 2026 -
100,000 USD - 166,750 USD for Level 1, a… 14 Oct 2026 -
100,000 USD - 166,750 USD for Level 1, a… 14 Oct 2026 -
13 Oct 2026 -
$95,000-$142,000 13 Oct 2026 -
13 Oct 2026 -
$166000-$248000 10 Oct 2026 -
$116,000 - $189,750 USD 10 Oct 2026 -
$165000-$248000 8 Oct 2026 -
8 Oct 2026 -
$98,000-$147,000 8 Oct 2026
SystemVerilog skills: Salary range
From 156 disclosed salaries.
Low
$70k
Median
$184k
High
$367k
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Top companies hiring SystemVerilog
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Top SystemVerilog roles
- ASIC Verification Engineer 13
- Senior Verification Engineer 9
- Sr. Staff Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR) 5
- Senior ASIC Verification Engineer 5
- Verification Engineer 4
- ASIC Engineer 3
- Applications Engineering, Sr Engineer 3
- Senior FPGA Verification Engineer 3
- Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) 3
- Principal Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR) 3
SystemVerilog jobs by city
- Bengaluru 54
- Santa Clara 24
- Hyderabad 17
- Sunnyvale 12
- Austin 10
- Bristol 6
- Shanghai 5
- Roseville 4
- Mississauga 4
- Dublin 4
- Costa Mesa 4
- San Francisco 3