Description
We are seeking a highly experienced design verification engineer with deep expertise in verifying complex digital IP and high-speed interfaces. You will develop and execute verification strategies for PHY, DDRIO, UCIe, and other high-speed interface IP. You will also architect and develop SystemVerilog/UVM testbenches, verification environments, test plans, and reusable verification components.
Responsibilities:
- Develop and execute verification strategies for PHY, DDRIO, UCIe, and other high-speed interface IP.
- Architect and develop SystemVerilog/UVM testbenches, verification environments, test plans, and reusable verification components.
- Create directed and constrained-random tests, assertions, functional coverage, and coverage models.
- Drive functional and code coverage closure, regression analysis, and verification signoff.
- Debug complex RTL, protocol, testbench, and system-level issues in partnership with design engineers.
- Verify block- and subsystem-level functionality, including interfaces, resets, clocking, low-power behavior, and error scenarios.
- Collaborate closely with RTL design, architecture, firmware, modeling, and implementation teams.
- Mentor engineers and help drive verification methodology and best practices.
Requirements:
- BS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience, or MS with 10+ years of experience.
- Strong experience in ASIC/IP design verification.
- Advanced proficiency with SystemVerilog and UVM.
- Experience developing verification environments, test plans, assertions, functional coverage, and constrained-random tests.
- Strong RTL and waveform debugging skills.
- Experience with PHY, DDR/DDRIO, UCIe, SERDES, PCIe, CXL, or similar high-speed interface technologies.
- Understanding of the complete ASIC/IP development and verification lifecycle.
- Strong analytical, problem-solving, and communication skills.
Benefits:
- Comprehensive medical and healthcare plans.
- Time away programs, including ETO and FTO.
- Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- ESPP, allowing purchase of Synopsys common stock at a 15% discount.
- Retirement plans that vary by region and country.