Description
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
As a Senior Principal ASIC Design Engineer, you will play a crucial role in defining, designing, and implementing high-speed ASICs from product requirements and architecture through final netlist. You will work on complex, high-impact subsystems, collaborate with system design teams across geographies, and have significant opportunities to shape both product capability and engineering methodology.
Responsibilities:
- Serve as the technical lead for a significant subsystem within a high-performance networking ASIC, defining the architecture from the ground up and translating product, hardware, and software requirements into a detailed and executable subsystem specification.
- Partner with product marketing, hardware, software, verification, and physical design teams to evaluate feasibility, make informed trade-offs, and deliver a design that meets power, area, performance, timing, and feature objectives.
- Author clear and comprehensive functional and micro-architecture specifications for assigned modules and subsystems.
- Implement complex RTL modules and subsystems using Verilog or SystemVerilog, with attention to quality, maintainability, timing closure, and design reuse.
- Develop functional coverage and SystemVerilog Assertions to support verification quality and help identify corner-case bugs early in the design cycle.
- Apply state-of-the-art power reduction techniques during architecture and implementation to ensure the design meets aggressive power targets.
- Collaborate closely with the physical design team on floorplanning, timing closure, and RTL-level timing fixes required to achieve frequency targets.
- Work with the verification team to ensure the assigned block or subsystem is fully validated against functional, performance, and integration requirements.
- Provide technical leadership, guidance, and mentoring to engineers across the design team.
- Drive continuous improvement of design methodologies through advanced EDA flows, automation, power optimization techniques, and disciplined design review practices.
- Champion automation and AI-assisted design methodology, including practical use of AI agents, AI skills, scripts, and workflow orchestration to accelerate specification development, RTL quality checks, debug, documentation, and design closure.
- Lead architecture-level trade-off discussions across major ASIC subsystems, ensuring that feature definition, performance, power, area, timing, verification, software, and physical design considerations are balanced from concept through tape-out.
Education and Experience Required:
- Bachelor’s degree in Electrical Engineering or a related field is required; a Master’s degree is preferred.
- Candidates should have 15+ years of relevant ASIC design experience.
Knowledge and Skills:
- Strong analytical, problem-solving, and technical decision-making skills.
- Demonstrated experience architecting and implementing high-performance ASIC subsystems from specification through final netlist.
- Prior first-authored patents in networking or computer architecture are a plus.
- Proven technical leadership experience, preferably as a chip lead or subsystem lead on prior ASIC development programs.
- Experience in at least two of the following areas: 10G–800G Ethernet interface standards; HBM2, HBM2E, DDR4, or related memory technologies and integration; security protocols such as MACsec and IPsec; networking protocols and deep packet inspection; schedulers; queuing and memory subsystems; and fixed-function or microcode-based packet processing.
- Strong coding skills in Verilog and SystemVerilog, demonstrated through prior ASIC implementation experience.
- Knowledge of synthesis, lint, CDC, formal, and other advanced EDA tools used in a modern ASIC development flow is highly desired.
- Familiarity with AI agents, AI skills, and automation frameworks that improve ASIC design productivity, design-space exploration, documentation quality, and review efficiency is strongly desired.
- Broad understanding of ASIC architecture, including front-end design, subsystem integration, verification interfaces, timing, power, area trade-offs, and production tape-out execution.
- Excellent written and verbal communication skills.
- Working knowledge of Perl and Python is strongly desired.
Benefits:
- Comprehensive suite of benefits that supports physical, financial, and emotional wellbeing.
- Investment in career development and growth.
- Unconditional inclusion and celebration of individual uniqueness.