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From the employer's careers site First seen 2 Nov 2026

ASIC Engineer

Cisco entry full-time

Salary

$107,800 - $157,400 per year

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Description

The Silicon One team at Cisco creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.

As an ASIC Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You will collaborate closely with verification engineers, designers, hardware, and other cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up to help guarantee seamless integration and optimal performance of Cisco’s hardware platforms.

Responsibilities:

  • Maintaining existing DV environments and enhancing them
  • Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks
  • Write test plan, develop test cases, debug regression failures and drive to module verification closure
  • Ensuring complete verification coverage through implementation and review of code and functional coverage

Minimum Qualifications:

  • A Bachelor's degree (completed within the past 3 years or expected to be completed within the next 12 months)
  • Qualifying education and work experience should be in ASIC Design, Design Verification, or a related field
  • Experience with System Verilog and UVM methodology
  • Experience with scripting using Perl and/or Python

Preferred Qualifications:

  • Experience using UVM and SystemVerilog for ASIC verification and verifying complex blocks and/or clusters within ASICs
  • Experience with functional coverage and constrained random DV environments
  • Experience in verifying complex blocks, clusters and top level for SoC
  • Experience with Veloce/HAPS
  • Experience building test benches from scratch, including experience in SystemVerilog constraints, structures, and classes
  • Effective verbal and written communication skills

Benefits:

  • Medical, dental and vision insurance
  • 401(k) plan with a Cisco matching contribution
  • Paid parental leave
  • Short and long-term disability coverage
  • Basic life insurance
  • Paid time away (10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees, 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness)
  • Optional 10 paid days per full calendar year to volunteer

Salary Range: $107,800.00 - $157,400.00 (New York City Metro Area) $94,800.00 - $140,000.00 (Non-Metro New York state & Washington state)

Skills

Required

  • System Verilog
  • UVM methodology
  • Perl
  • Python
  • ASIC Design
  • Design Verification

Nice to have

  • UVM
  • SystemVerilog
  • functional coverage
  • constrained random DV environments
  • Veloce/HAPS
  • SystemVerilog constraints
Apply on Cisco