Description
We are seeking an experienced ASIC Design Verification Engineer to join our team in Bengaluru, Karnataka, India. As an ASIC Design Verification Engineer, you will play a critical role in designing, analyzing, developing, modifying, and evaluating VLSI components and hardware systems.
Job Description:
- Develop and enhance ASIC verification environments using the latest methodologies such as UVM.
- Architect and build block-level, subsystem, and full-chip verification environments using SystemVerilog and UVM.
- Define, design, and execute verification suites and test cases for complex ASICs using front-end simulators such as VCS and NC.
- Independently verify large ASIC blocks and drive tape-out readiness through code coverage, functional coverage, and gate-level simulation analysis.
- Collaborate with logic designers to debug and resolve design issues, and work with software teams during bring-up and validation.
- Develop Perl, Python, and/or Shell scripts to improve verification infrastructure, automation, and methodology.
Requirements:
- Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE).
- 5+ years of experience in ASIC Verification.
- Strong experience with SystemVerilog for ASIC verification.
- Experience with constrained-random verification techniques.
- Hands-on experience with industry-standard verification methodologies such as OVM, VMM, or UVM.
- Proficiency in Perl, Tcl, Python, or Shell scripting (Perl/Tcl preferred).
- Experience verifying networking protocols such as Ethernet is a plus.
- Strong problem-solving, debugging, and ASIC verification skills.
- Excellent analytical and collaboration skills.