Description
We are seeking a Senior System Verification Engineer to join our Emulation division at NVIDIA's Santa Clara, CA headquarters.
As a Senior System Verification Engineer, you will be working on multiple emulation environments using the latest emulation techniques, including C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, and Accelerated UVM Testbenches.
Your responsibilities will include:
- Bringing up GPUs, SOCs, Switch, NIC on emulation, and root causing system-level test fails and emulator environment issues.
- Bringing up and verifying High-Speed protocols like PCIe/CXL/NVLINK/IB/Ethernet, as well as low-speed protocols like I2C/I3C/SPI/UART.
- Debugging issues related to CPU and GPU Coherency.
- Collaborating with Design, DV, Power, Silicon Validation, Performance, and Software teams.
- Working with emulation vendors to debug issues using various tools.
- Writing monitors and checkers that aid in debugging HW test issues and FW/SW bring-up.
To be successful in this role, you will need:
- M.S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering, or a related field with 8+ years of proven experience.
- Proficiency in Verilog and/or VHDL, C/C++, and SystemVerilog.
- Protocol knowledge of at least one High-speed interface: PCIe/CXL/NVLINK/IB/Ethernet, etc.
- Knowledge of low-speed protocols like I2C/I3C/SPI/UART and BMC interaction in server platforms.
- Working knowledge of CPU-GPU coherency.
- Experience with UVM verification environments and scripting with Perl, Python, and C/C++.
- Familiarity with hierarchical design approaches, top-down design, SoC, and system-level verification.
- Zebu emulation experience with SOC/CPU.
In terms of compensation, the expected base salary ranges for this position are: 168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5. You will also be eligible for equity and benefits.