Description
We are seeking a highly motivated Senior ASIC Verification Engineer to join our networking silicon development team.
As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex modules and subsystems where you can challenge yourself and grow.
Key Responsibilities:
- Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
- Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
- Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
- Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
- Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.
Required Skills and Qualifications:
- 15+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
- Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
- Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
- Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
- Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.
Preferred Skills and Experience:
- Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
- Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
- Exposure to emulation environments, hardware acceleration, or traffic-model integration.
- Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).
- Understanding of low-power (UPF) or formal verification methodologies.
- Experience with post-silicon bring-up and debug is a plus.
- Familiarity with emulation environments and debug flows is desirable.
What We Can Offer You:
- Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
- Personal & Professional Development: We also invest in your career because the better you are, the better we all are.
- Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness.