Description
This is a hybrid role with four days per week at Cisco’s Yerevan office.
The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.
Your Impact: Develop and execute comprehensive testbenches to verify DFT architectures, ensuring thorough coverage across complex silicon design specifications. Collaborate cross-functionally with ASIC design and verification teams to integrate, simulate, and debug test logic throughout the implementation flow. Implement robust DFT methodologies across emerging silicon models, including scan chains, MBIST, and in-system test structures. Analyze and resolve verification bottlenecks using industry-standard debug tools to deliver clean test patterns and meet critical tapeout milestones. Your contributions will directly enhance silicon testability, debug efficiency, and product reliability across Cisco's next-generation networking hardware.
Minimum qualifications:
- Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 5+ years of professional experience in design verification, DFT verification, or ASIC design.
- Proven experience in test planning, testbench execution, and coverage closure based on complex design specifications.
- Hands-on proficiency in waveform debugging and simulation using tools such as Verdi or DVE.
- Strong scripting skills in Python, Tcl, or Perl for verification automation and test flow execution.
Preferred qualifications:
- Hands-on experience in testbench development using SystemVerilog and UVM.
- Solid knowledge of DFT structures including IEEE 1149.1 JTAG, scan compression, MBIST, and boundary scan.
- Exposure to advanced FinFET process nodes and post-silicon validation or ATE bring-up support.
- Proactive problem-solving skills with the ability to manage tasks independently and resolve verification blockers.
- Strong cross-functional communication skills and enthusiasm for onsite collaboration in a fast-paced engineering team.