Description
We are seeking a Senior AIML enhanced Design/Verification Methodology Engineer to join our team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs using AIML enhanced methodologies.
You will architect, build, and maintain AIML enhanced or agentic solutions for design and verification environments with applications to all phases of design and verification closure. You will collaborate closely with design and system engineering teams to ensure silicon quality from RTL to tapeout.
Key Responsibilities
- Use both 'classical' and Generative-AI methodologies to architect, develop, and maintain agents, skills, and other AI-based design and verification infrastructures.
- Create UVM-based testbench environments from ground up or enhance existing ones using AI.
- Create verification plans with clear coverage goals and closure criteria.
- Perform root cause analysis of failures and work with design teams to drive resolution.
- Automate generation of RTL from spec.
- Evaluate industry tools.
Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent).
- 3-5 years of direct hands-on experience with AIML methods, concepts, and workflows.
- 5-7 years of experience in production development of RTL design and verification infrastructure.
- Strong experience in SystemVerilog for design or verification.
- Solid understanding of digital design fundamentals (RTL, timing, synthesis constraints).
- Experience with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
- Effective communication and collaboration skills in cross-functional team settings.
Preferred Qualifications
- Master's or Ph.D. in Electrical Engineering or Computer Science.
- Experience with formal verification tools and techniques (e.g., JasperGold, VC Formal).
- Experience with emulation and FPGA prototyping platforms (e.g., Palladium, Protium, Veloce).
- Industry conference/peer-reviewed journal publications in design/verification methodology development and/or AIML.
Benefits
- Competitive compensation
- Comprehensive benefits
- Opportunities for professional growth