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SystemVerilog jobs
14 employers are hiring for 220 live roles that ask for SystemVerilog, with Bengaluru, Santa Clara and Hyderabad the busiest cities, and where pay is shown, the median is $184k. Browse them all, filter by location or remote, or set a free alert for new ones.
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Live roles
220
Employers
14
Median salary
$184k
Locations
61
Filters
Work type
Experience
220 roles
Latest roles
220 jobs · page 3 of 5
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168,000 USD - 264,500 USD for Level 4, a… 8 Oct 2026 -
Senior Staff Verification Engineer, High-Speed InterconnectOn-site senior7 Oct 2026 -
Principal ASIC Digital Design Engineer (Verification)On-site senior7 Oct 2026 -
7 Oct 2026 -
7 Oct 2026 -
7 Oct 2026 -
7 Oct 2026 -
7 Oct 2026 -
Digital Design Verification, Principal EngineerOn-site senior7 Oct 2026 -
$20-$71 per hour 7 Oct 2026 -
$20-$71 per hour 7 Oct 2026 -
6 Oct 2026 -
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136,000 USD - 218,500 USD for Level 3, a… 2 Oct 2026 -
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1 Oct 2026 -
1 Oct 2026 -
Sr Staff Mixed-Signal Verification EngineerOn-site senior30 Sept 2026 -
30 Sept 2026 -
38 USD - 94 USD 29 Sept 2026 -
28 Sept 2026 -
28 Sept 2026 -
100,000 USD - 166,750 USD for Level 1, a… 28 Sept 2026 -
100,000 USD - 166,750 USD for Level 1, a… 28 Sept 2026 -
$166000-$249000 28 Sept 2026 -
26 Sept 2026 -
26 Sept 2026 -
$1,925-$1,925 USD 24 Sept 2026 -
24 Sept 2026 -
23 Sept 2026 -
168,000 USD - 264,500 USD for Level 4, a… 23 Sept 2026 -
22 Sept 2026 -
22 Sept 2026 -
22 Sept 2026 -
22 Sept 2026 -
21 Sept 2026 -
$146000-$219000 21 Sept 2026 -
$129000-$193000 19 Sept 2026 -
$157000-$235000 19 Sept 2026 -
$157000-$235000 19 Sept 2026 -
$184000-$276000 19 Sept 2026 -
$112,000-$168,000 18 Sept 2026 -
$157000-$235000 18 Sept 2026 -
$129000-$193000 18 Sept 2026 -
$160000-$240000 18 Sept 2026 -
18 Sept 2026 -
$146000-$219000 18 Sept 2026 -
17 Sept 2026 -
17 Sept 2026 -
$147000-$220000 17 Sept 2026
SystemVerilog skills: Salary range
From 156 disclosed salaries.
Low
$70k
Median
$184k
High
$367k
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Top SystemVerilog roles
- ASIC Verification Engineer 13
- Senior Verification Engineer 9
- Sr. Staff Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR) 5
- Senior ASIC Verification Engineer 5
- Verification Engineer 4
- ASIC Engineer 3
- Applications Engineering, Sr Engineer 3
- Senior FPGA Verification Engineer 3
- Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) 3
- Principal Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR) 3
SystemVerilog jobs by city
- Bengaluru 54
- Santa Clara 24
- Hyderabad 17
- Sunnyvale 12
- Austin 10
- Bristol 6
- Shanghai 5
- Roseville 4
- Mississauga 4
- Dublin 4
- Costa Mesa 4
- San Francisco 3