Description
You will work as a Sr Staff Applications Engineer, HAV Solutions at Synopsys, a leading provider of engineering solutions from silicon to systems. The role involves leading technical deployments of HAPS-200 and ProtoCompiler for strategic customers building billion-gate SoCs across AI/ML, automotive, hyperscaler, and aerospace segments.
You have spent years moving between RTL, FPGAs, and real hardware, and you know that the gap between a design that compiles and one that actually boots is where most projects stall. You understand partitioning tradeoffs, clock domain crossings, and why a PCIe link trains in simulation but fails on the board.
Your responsibilities will include:
- Leading technical deployments of HAPS-200 and ProtoCompiler for strategic customers
- Driving the full ASIC-to-FPGA flow including partitioning, clock conversion, synthesis, place-and-route, timing closure, bitstream generation, and hardware bring-up on multi-FPGA systems
- Debugging complex interface IP subsystems including DDR4/DDR5, LPDDR5/6/7, HBM, PCIe Gen3-6, CXL, UCIe, Ethernet, USB, AXI, and high-speed SerDes architectures
- Reproducing, analyzing, and resolving critical customer escalations involving RTL issues, partitioning failures, timing violations, protocol mismatches, and hardware bring-up failures
- Collaborating directly with ProtoCompiler R&D and Product Management to validate new features, influence roadmap priorities, and represent customer requirements in product planning
The impact you will have includes:
- Enabling customers to prototype and validate complex SoCs months earlier by solving partitioning, timing, and bring-up challenges
- Influencing the ProtoCompiler roadmap and feature set based on direct engagement with the most demanding semiconductor and systems customers
- Reducing critical customer escalations by building repeatable debug methodologies and training global teams on advanced troubleshooting techniques
Requirements include:
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience
- 10+ years working in FPGA implementation, ASIC design, ASIC verification, hardware-assisted verification, FPGA prototyping, or emulation
- Deep expertise in FPGA synthesis, place-and-route, multi-FPGA partitioning, timing closure, and constraint development using Xilinx Vivado, Intel Quartus, or equivalent tools
- Strong working knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification testbench architecture
Rewards and benefits include a comprehensive range of health, wellness, and financial benefits.