Description
We are seeking an experienced ASIC Verification Engineer who is passionate about solving complex protocol challenges and delivering world-class Interface IP solutions.
In this role, you will work on industry-leading PCIe, CXL, DDR, and Ethernet technologies that serve as foundational building blocks for AI accelerators, data centers, networking platforms, and next-generation SoCs. You will collaborate with architects, design engineers, and verification experts to ensure the quality, performance, and reliability of technology used by leading semiconductor companies worldwide.
Responsibilities
- Own verification of complex Interface IP solutions, including PCIe, CXL, DDR, and Ethernet technologies.
- Architect, develop, and enhance scalable UVM-based verification environments and reusable verification IP.
- Define verification strategies and test plans from specification review through product release.
- Develop constrained-random, coverage-driven verification solutions using SystemVerilog and UVM.
- Drive functional coverage closure and verification signoff activities.
- Debug challenging RTL, protocol, and system-level issues while improving verification efficiency and automation.
- Partner closely with architecture, RTL, firmware, and systems teams to identify issues early and ensure robust product quality while also mentoring engineers contributing to verification methodology improvements across the organization.
Requirements
- BSEE with at least 8 to 10+ years of direct industry experience with proven experience verifying complex ASIC or SoC designs.
- Deep expertise with SystemVerilog and UVM methodologies.
- Strong protocol knowledge in one or more of the following areas: PCI Express (PCIe), Compute Express Link (CXL), DDR Memory Interfaces, Ethernet.
- Experience developing constrained-random and coverage-driven verification environments.
- Strong debugging and problem-solving skills spanning RTL, verification, and protocol compliance.
- Experience with industry-standard simulators such as VCS, ModelSim, or similar tools.
- Ability to independently drive technical initiatives while collaborating across geographically distributed teams.
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
This listing is enriched and indexed by YubHub. To apply, use the employer's original posting:
https://careers.synopsys.com/job/austin/senior-principal-interface-ip-verification-engineer-pre-silicon-18386/44408/99263061744