Principal ASIC Digital Design Engineer (Verification)

You are a seasoned verification engineer with over a decade of experience, skilled in architecting and implementing unified verification flows for digital IP products. You will lead the design and implementation of scalable verification infrastructure, define and propagate verification methodologies, and mentor junior engineers.

Key Responsibilities:

• Architect and implement unified verification flows for Synopsys digital IP products using VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs
• Build scalable verification infrastructure from the ground up, designing environments that support complex IP and SoC projects across global teams
• Define, document, and propagate verification methodologies and best practices that become the standard across Synopsys digital IP projects
• Lead and mentor verification engineers, providing technical guidance on UVM, SystemVerilog, flow optimization, and debugging strategies

The Impact You Will Have:

• Establish verification methodology standards that accelerate time-to-market for Synopsys digital IP and SoC products
• Enable global verification teams to deliver higher quality results faster by providing robust, reusable flows and infrastructure
• Shape the verification strategy for next-generation Synopsys IP offerings, directly influencing product quality and customer satisfaction

Requirements:

• 10+ years of hands-on experience in IP or SoC verification, with a proven track record of leading technical initiatives and delivering complex verification environments
• Deep expertise with Synopsys verification tools including VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and Verification IP (VIP)
• Strong programming and scripting skills in SystemVerilog, UVM, Tcl, and Python for automation and flow development