Description
You will be a Verification Applications Engineer at Synopsys, working directly with customers to support their verification needs. Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products.
Your role involves supporting customers using Synopsys verification tools like VCS and Verdi, diagnosing simulation issues, debug challenges, and coverage gaps in their design flows. You will analyze customer testbenches and design environments to identify root causes of verification failures and propose technical solutions that fit their methodology.
Key responsibilities include:
- Supporting customers with Synopsys verification tools
- Analyzing customer testbenches and design environments
- Working on verification challenges involving SystemVerilog, UVM, low power verification, and coverage-driven workflows
- Collaborating with Synopsys R&D teams to escalate complex issues
- Building scripts in Tcl, Python, or Perl to automate workflows
- Guiding customers through tape-out cycles
The impact of your work will be:
- Directly reducing time to tape-out for customers
- Helping design teams adopt better debug and coverage practices
- Influencing product roadmaps by surfacing real customer pain points
- Enabling customers to verify complex, multi-million gate designs with confidence
Requirements:
- Bachelor's degree in Electronics Engineering or related field with 2+ years of experience in verification or digital design
- Strong fundamentals in digital design and hands-on experience with Verilog or VHDL
- Working knowledge of SystemVerilog and dynamic simulation concepts
- Proficiency in UNIX or Linux environments and scripting with Tcl, Python, or Perl
- Excellent written and verbal communication skills
Rewards and benefits include a comprehensive range of health, wellness, and financial benefits.