ASIC Verification Engineer, Staff Level

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years in verification trenches where the difference between a clean signoff and a late-stage respin comes down to the testbench you built three months ago. You know that coverage numbers mean nothing if the corner cases are still hiding, and you are the engineer who finds them before tapeout. You think in layers: block-level behavior, subsystem integration, protocol compliance, and the edge cases that only show up when three things go wrong at once.

Working in UVM is second nature to you. You do not just write tests, you build environments that catch real bugs and make the next verification cycle faster. Debugging is not a chore for you, it is a puzzle you actually enjoy solving, whether that means tracing through waveforms at 2am or writing a Python script to parse regression logs and surface the pattern everyone else missed.

You have worked on real IP, the kind that ships in millions of devices, and you understand what it takes to get from "mostly works" to "ready for customer integration."

What You'll Be Doing

• Verify IP blocks and subsystems across DesignWare product lines, developing and executing verification plans, test scenarios, checkers, assertions, and functional coverage models for your assigned areas
• Build and enhance UVM-based verification environments that support block-level and subsystem-level testing, regression automation, and coverage closure
• Debug complex functional failures across IP domains like Ethernet, USB, PCI Express, or other industry-standard protocols, identifying root causes and driving resolution with design and architecture teams
• Analyze regression results, track coverage metrics, and identify gaps or risks that could affect signoff quality or schedule
• Write scripts and automation utilities in Python or similar languages to improve debug efficiency, regression analysis, test development, and coverage closure
• Collaborate with cross-functional teams including design, firmware, quality, and architecture to clarify requirements, resolve technical issues, and align on verification strategy
• Apply AI-assisted techniques where appropriate to accelerate debug workflows, optimize regression cycles, or improve test generation and coverage analysis

The Impact You Will Have

• Deliver high-quality, customer-ready DesignWare IP by catching critical bugs early and ensuring thorough verification coverage across your assigned blocks and subsystems
• Reduce time-to-signoff by building reusable verification infrastructure, improving regression efficiency, and identifying risks before they become schedule blockers
• Strengthen the quality and reliability of Synopsys IP that powers next-generation AI, mobile, automotive, and data center silicon products used by customers worldwide
• Enable faster debug and root cause analysis across the team by developing automation tools, sharing technical knowledge, and improving verification workflows
• Support predictable project execution by maintaining clear verification plans, tracking progress against coverage and quality goals, and communicating risks early
• Contribute to Synopsys leadership in the era of pervasive intelligence by helping verify the IP building blocks that enable advanced AI and compute architectures
• Improve team execution and engineering practices through dependable collaboration, peer reviews, documentation, and knowledge sharing

What You'll Need

• Bachelor's or Master's in Electrical, Electronics, or Computer Engineering with 5+ years of hands-on IP or SoC verification experience (or MS with 3+ years)
• Strong proficiency in SystemVerilog and UVM, VMM, or OVM methodologies, with real project experience developing verification environments, test plans, checkers, assertions, and functional coverage
• Hands-on experience with industry-standard simulators such as VCS and associated debug tools, including waveform analysis and regression infrastructure
• Demonstrated ability to debug complex functional failures, analyze regression results, track issues to closure, and support verification signoff activities
• Experience writing scripts or automation utilities in Python, Perl, or shell to improve verification productivity, debug efficiency, or regression analysis
• Practical understanding of verification planning, coverage analysis, quality criteria, and what it takes to reach signoff on real IP or SoC projects
• Experience with DesignWare IP or similar synthesizable IP verification projects is a strong plus, as is familiarity with protocols such as Ethernet, USB, or PCI Express
• Exposure to AI-assisted methods for debug, regression optimization, test generation, or coverage closure is desirable

Rewards and Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries