Applications Engineering, Sr Engineer Engineer

You will be part of the Korea-based Applications Engineering team supporting Synopsys verification solutions. As an Applications Engineering, Sr Engineer Engineer, you will provide technical support and consultation to customers using VCS simulator and Verdi debug platform, resolving issues that range from setup and configuration to complex simulation performance bottlenecks.

You have spent years deep in verification, the kind where you know that a clean testbench is only half the battle and the other half is figuring out why a simulation that should take two hours is taking twelve. You have debugged enough UVM environments to spot a misconfigured factory override from three files away, and you have worked with UPF long enough to know that low-power intent and actual low-power behavior are not always the same thing.

Your responsibilities will include:

• Providing technical support and consultation to customers using VCS simulator and Verdi debug platform
• Engaging directly with customer verification teams to optimize their workflows, improve regression efficiency, and troubleshoot testbench and UVM environment issues
• Delivering best practices and methodology guidance for SystemVerilog, UVM, and low-power verification using UPF
• Developing scripts, automation flows, and technical documentation that help customers adopt and scale Synopsys verification tools across their projects
• Debugging complex simulation and verification challenges
• Collaborating with internal R&D, field engineering, and product teams to escalate issues, share customer feedback, and contribute to product improvements

The impact you will have:

• Customers will close verification faster because their simulation runs are optimized and their debug cycles are shorter
• Verification teams will adopt UVM and low-power methodologies more confidently
• Complex technical escalations will get resolved
• Synopsys tools will be used more effectively across Korea's semiconductor ecosystem
• Internal product teams will build better features because you brought them real-world customer feedback and use cases

To be successful in this role, you will need:

• 5–10 years of hands-on experience in ASIC or SoC verification
• Strong proficiency in Verilog, SystemVerilog, and UVM methodology
• Hands-on experience with UPF and low-power verification
• Demonstrated ability to debug complex simulation issues
• Experience with VCS, Verdi, or other industry-standard simulation and debug tools is a strong plus
• Familiarity with scripting languages like Python, Tcl, or shell scripting for automation and flow development
• Ability to communicate technical concepts clearly in both Korean and English