Staff Digital Verification Engineer

Overview

You will work as a Staff Digital Verification Engineer at Synopsys, a leading provider of engineering solutions from silicon to systems. Your role will involve designing and developing cutting-edge semiconductor solutions, focusing on verification environments for DesignWare synthesizable IP cores.

Job Description

You have spent years building verification environments that have to catch the bugs no one else saw coming. You know that a test plan is only as good as the bugs it finds, and you have learned to think like the design, like the system integrator, and like the customer all at once.

What You'll Be Doing

• Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations and configurations
• Define comprehensive test plans that cover corner cases, protocol compliance, and system-level interactions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable
• Write and debug complex testbenches, checkers, and assertions that catch real bugs in critical PHY blocks and interface logic
• Develop software requirements for the PHY that scale across various configurations and use cases
• Own verification closure for multiple critical blocks within DDR PHYs, including functional coverage, code coverage, and formal signoff
• Collaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design intent and surface issues early in the design cycle
• Manage regression infrastructure and work with the infra team to optimize verification cycles, debug failures, and keep the environment reliable

The Impact You Will Have

• Your verification environments will catch critical bugs before tapeout, directly affecting the quality and time-to-market of DesignWare IP used across the semiconductor industry
• The test plans you define and review will set the verification standard for the team, ensuring consistent coverage and reducing escapes
• Your coverage-driven approach will surface gaps that others miss, leading to more robust IP and fewer silicon respins
• The assertions and checkers you write will become reusable verification IP, accelerating future projects and raising the quality bar
• Your collaboration with RTL and architecture teams will shape design decisions early, making designs easier to verify and more reliable in the field
• The regression strategies you implement will directly improve team productivity and reduce verification cycle time
• Your ownership of critical PHY blocks will ensure that high-stakes features meet functional and performance requirements on schedule

What You'll Need

• Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 4+ years of hands-on verification experience
• Proven track record leading verification teams through IP project delivery, including planning, execution, and signoff
• Strong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow in complexity
• Deep expertise writing test plans, implementing checkers, and building assertions that catch real bugs, not just toggle coverage
• Proficiency extracting and interpreting functional coverage and code coverage metrics, and using those insights to drive verification closure
• Experience verifying serial interface protocols and working through IP design and verification processes, knowledge of DDR or LPDDR protocols is a strong plus
• Demonstrated ability to own end-to-end verification deliverables, including metric closure and formal review signoff, experience with AI-assisted verification tools is a plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away programs, including ETO and FTO
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans that vary by region and country
• Competitive salaries