Description
We are looking for a best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team. As a Senior Physical Design Engineer, you will be responsible for the physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Your daily work will involve all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. You will also take part in flow development and act as Partition/Unit level physical design technical leader and focal point.
To succeed in this role, you will need a B.SC./M.SC. in Electrical Engineering/Computer Engineering, 5+ years of experience in physical design, proven experience in RTL2GDS flows and methodologies, knowledge in physical design flows and methodologies (PNR, STA, physical verification), familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.), and great teamwork skills.