Synopsys

Digital Design Verification – Application Engineer

Synopsys
onsite senior full-time Reading
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First indexed 5 Apr 2026

Description

Job Overview

You will work closely with customers, Sales, R&D, and field teams to help them adopt and deploy Synopsys Verification solutions.

Responsibilities

  • Engage directly with customers to understand their verification needs
  • Support pre-sales activities: demos, technical evaluations, benchmarks, methodology guidance
  • Improve customer verification flows and testbench architectures
  • Debug RTL/gate-level simulation issues and SystemVerilog/UVM environments
  • Analyse functional and code coverage
  • Develop and debug SystemVerilog assertions
  • Collaborate with Sales to grow adoption and identify new opportunities
  • Act as the technical voice of the customer to R&D

Requirements

  • Typically requires 8–13 years of relevant experience
  • Strong knowledge of Verilog/SystemVerilog, UVM, coverage, and assertions
  • Experience in customer interaction, pre-sales, or technical support is a plus
  • Strong problem-solving and communication skills
  • Bachelor’s degree in Computer Engineering, Electrical Engineering, or related field

The Team You’ll Be A Part Of

You’ll join a dynamic, Theale based Customer Application Services team dedicated to delivering world-class technical support and solutions for leading semiconductor companies.

This listing is enriched and indexed by YubHub. To apply, use the employer's original posting: https://careers.synopsys.com/job/reading/digital-design-verification-application-engineer/44408/91405850656