Description
Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.
You are a passionate Computer Scientist with an exceptional analytical mind, driven by curiosity and a desire to solve some of the most challenging problems in automated logical reasoning and symbolic computation. You thrive in intellectually stimulating environments, enjoying the pursuit of innovative solutions within deep technology domains. Your expertise spans formal methods, algorithms, and complexity theory, enabling you to tackle large-scale, industrial verification challenges with confidence and creativity.
You bring hands-on experience in developing robust software solutions, particularly in C/C++. Whether your background is academic or industry, your contributions have been recognized by peers, and you are eager to collaborate with leading experts in the field. You understand the nuances of hardware architecture and design languages like SystemVerilog, or you are enthusiastic to learn them, appreciating their impact on verification excellence.
You are adaptable, open to new ideas, and motivated by continuous learning. You value diversity of thought, enjoy working in collaborative teams, and are committed to advancing the state of the art in formal verification. You believe in the transformative power of AI/ML-assisted design flows and are excited to shift the paradigm from design-centric to verification-centric innovation. Above all, you are ready to make a significant impact in the future of technology by joining the Synopsys Formal Technology Group.
Designing and implementing advanced formal verification algorithms and proof engines for large-scale VLSI chip designs. Developing scalable, memory-efficient, and mathematically robust solvers to address industry-leading verification challenges. Integrating innovative solutions into the Synopsys VC Formal platform, enhancing its capabilities and usability for thousands of engineers worldwide. Collaborating with cross-functional teams to extend formal verification technologies into domains such as hardware security, functional safety, and low power. Engaging with customers and industry partners to understand their verification needs and deliver best-in-class solutions. Contributing to the formal verification community through peer-reviewed publications, technical presentations, and mentorship of junior team members.
Advancing the scalability and reliability of formal verification tools used by leading chip design companies. Breaking complexity barriers, enabling verification of the most challenging and extensive industrial designs. Driving innovation in AI/ML-assisted design flows, transforming the verification landscape for the semiconductor industry. Empowering customers to achieve functional safety, hardware security, and low power goals in their products. Facilitating widespread adoption of formal methods across diverse domains and applications. Fostering a collaborative, intellectually rich environment that inspires continuous learning and knowledge sharing.
8-10 years of relevant experience Expertise in formal methods, model checking, theorem proving, and equivalence checking. Strong proficiency in algorithms, data structures, and complexity analysis. Professional coding skills in C/C++ and experience developing large-scale software systems. Background in hardware architecture and familiarity with design languages such as SystemVerilog (preferred but not required). Peer recognition in the formal verification community, such as publications or industry accolades.
Analytical thinker with a keen eye for detail and problem-solving. Collaborative team player who values diversity and open communication. Innovative and adaptable, willing to embrace new technologies and methodologies. Driven by curiosity and a passion for continuous learning. Resilient in the face of challenging technical problems and complexity.
You’ll join the Synopsys VC Formal R&D Team,a vibrant community of talent and expertise dedicated to advancing formal verification technologies. The team is renowned for solving deep theoretical and practical problems and integrating them into world-leading verification tools. You will collaborate with experts in formal methods, software engineering, and AI/ML, contributing to the proliferation of formal verification across hardware security, functional safety, low power, and more.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.