Description
You will be an experienced engineer with a passion for solving complex technical challenges and a deep interest in shaping the future of semiconductor design. This role involves designing and analysing algorithms for end-to-end timing constraint management across the Synopsys flow. You will drive the success and evolution of Synopsys' constraint flow and tools, enhancing product performance and integration.
Key responsibilities include designing and analysing algorithms for end-to-end timing constraint management, driving the success and evolution of Synopsys' constraint flow and tools, collaborating within a highly skilled engineering team to deliver innovative solutions for static timing analysis (STA) during design and optimisation, and designing, developing, troubleshooting, and debugging advanced software programs for constraint generation and verification.
The ideal candidate will have a B.Tech/M.Tech in Computer Science or Electrical Engineering from a reputed institute, 8 years of experience with strong foundational knowledge of programming fundamentals, including data structures, sorting, searching algorithms, and numerical methods, ability to read and analyse code in C/C++, exceptional debugging skills and proficiency in scripting languages (such as Python, Perl, or TCL), demonstrated analytical and problem-solving skills, with a keen attention to detail, independent judgment in selecting methods and techniques to obtain technical solutions, experience with Synopsys Static Timing Analysis (STA) tools and EDA tool/CAD flow development (preferred), and experience with Synopsys Design Constraints (SDC) is a strong plus.
This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. The total rewards include both monetary and non-monetary offerings.