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Verilog jobs
11 employers are hiring for 199 live roles that ask for Verilog, with Bengaluru, Santa Clara and Sunnyvale the busiest cities, and where pay is shown, the median is $190k. Browse them all, filter by location or remote, or set a free alert for new ones.
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Live roles
199
Employers
11
Median salary
$190k
Locations
54
Filters
Work type
Experience
199 roles
Latest roles
199 jobs · page 1 of 4
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4 Nov 2026 -
4 Nov 2026 -
Mission Analysis Engineer (Mid-career)On-site mid$108,800 - $160,000 3 Nov 2026 -
Hourly Salary USD 35.00 - 41.00 1 Nov 2026 -
Pre-Silicon Diagnostics & Validation EngineerHybrid senior$147,000 - $279,000 per year 1 Nov 2026 -
$167,700 - $245,200 1 Nov 2026 -
$186,900 to $267,700 1 Nov 2026 -
$87,100 - $157,450 1 Nov 2026 -
$95,800 - $139,700 1 Nov 2026 -
$35.00 - $41.00 per hour 1 Nov 2026 -
1 Nov 2026 -
31 Oct 2026 -
31 Oct 2026 -
31 Oct 2026 -
31 Oct 2026 -
31 Oct 2026 -
31 Oct 2026 -
196,000 USD – 310,500 USD for Level 5 31 Oct 2026 -
196,000 USD – 310,500 USD 31 Oct 2026 -
168,000 USD – 264,500 USD for Level 4 31 Oct 2026 -
152,000 USD – 241,500 USD for Level 3 31 Oct 2026 -
$122000-$183000 30 Oct 2026 -
30 Oct 2026 -
30 Oct 2026 -
30 Oct 2026 -
224,000 USD - 356,500 USD for Level 5, a… 30 Oct 2026 -
30 Oct 2026 -
29 Oct 2026 -
29 Oct 2026 -
$105,500 - $213,500 per year 29 Oct 2026 -
VLSI Design Verification InternHybrid entry$35.00 - $41.00 per hour 29 Oct 2026 -
Hardware Engineering InternOn-site entryHourly Salary USD 35.00 - 41.00 29 Oct 2026 -
ASIC Verification/Design Engineering InternHybrid entryHourly Salary USD 35.00 - 41.00 29 Oct 2026 -
$116,150 to $182,400 USD annually 29 Oct 2026 -
ASIC Verification Engineering InternHybrid entryHourly Salary USD 35.00 - 41.00 29 Oct 2026 -
Principal ASIC Design EngineerHybrid seniorAnnual Salary USD 181,000 - 367,000 29 Oct 2026 -
$35.00 - $41.00 per hour 29 Oct 2026 -
Senior Principal ASIC Design EngineerHybrid seniorAnnual Salary USD 181,000 - 367,000 28 Oct 2026 -
28 Oct 2026 -
$179,000 - $268,000 28 Oct 2026 -
28 Oct 2026 -
27 Oct 2026 -
27 Oct 2026 -
$160000-$240000 27 Oct 2026 -
27 Oct 2026 -
Hardware Design Engineer - PCB, Schematic, Physical DesignOn-site senior26 Oct 2026 -
26 Oct 2026 -
26 Oct 2026 -
26 Oct 2026 -
26 Oct 2026
Verilog skills: Salary range
From 150 disclosed salaries.
Low
$70k
Median
$190k
High
$431k
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Top Verilog roles
- Senior Verification Engineer 7
- Senior ASIC Design Engineer 4
- Verification Engineer 4
- ASIC Design Engineer 3
- Applications Engineering, Sr Engineer 3
- ASIC Digital Design Engineer 3
- Senior FPGA Verification Engineer 3
- Senior Mixed Signal Design Engineer 3
- ASIC Digital Design, Sr Staff Engineer 3
- ASIC Verification Engineering Intern 2
Verilog jobs by city
- Bengaluru 46
- Santa Clara 33
- Sunnyvale 14
- San Jose 8
- Shanghai 7
- Roseville 6
- Wuhan 5
- Ho Chi Minh City 5
- Costa Mesa 5
- Yerevan 4
- Seongnam-si 4
- Moreira 3