Description
ASIC Design Engineer 2 role at Hewlett Packard Enterprise's Juniper Silicon group, a leading provider of advanced routers and switches for the internet.
You will design high-speed ASICs, from specifications to final netlist, and have the opportunity to work on design, verification, or timing closure/PD.
Responsibilities:
- Create detailed micro-architecture specifications from functional specifications
- Perform RTL coding using System Verilog
- Write functional coverage/SVA
- Work on timing closure with PD to identify and fix timing issues in RTL
- Debug issues in your block found by the verification team
- Use state-of-the-art EDA tools for various design checks
Recommended skills:
- Bachelor's degree in Electrical Engineering required, Master's strongly desired
- Strong analytical/problem-solving skills
- Courses in digital logic design
- Strong coding skills in Verilog/System Verilog
- Knowledge of Computer Architecture, networking protocols, or machine learning is a plus
- Excellent written and verbal communications skills
- Knowledge of Perl/Python is a plus
The expected salary/wage range for this position is $105,500 - $213,500 per year.
HPE offers a comprehensive suite of benefits that supports physical, financial, and emotional wellbeing, as well as programs for personal and professional development.