Description
Join NVIDIA's Mixed Signal team in Santa Clara, CA, and contribute to the design of CMOS high-speed interface circuits and mixed-signal circuits. You will lead design projects, including high-speed transceivers and high-frequency PLLs, and work on silicon validation, debugging, characterization, and bring-up.
Key Responsibilities:
- Lead design and implementation of high-speed interface circuits
- Design, simulate, and verify mixed-signal circuits
- Supervise IC circuit/mask designers and provide floorplan and layout guidelines
- Support lab characterization of silicon
- Tackle challenges of circuit design in deep submicron CMOS
- Take designs through implementation and productization
- Work with multi-functional teams
Requirements:
- MS in Electrical Engineering or equivalent experience
- 4+ years of design experience in CMOS analog/mixed-signal circuit design
- Solid understanding of Cadence custom design tools, circuit simulator, and timing analysis tool
- Proven experience in crafting and mentoring designers
- Extensive experience in Tx, Rx, CDR, PLL for high-speed IO interfaces
- In-depth understanding of deep submicron CMOS process and related circuit design issues
- Experience in silicon bring-up, debugging, and use of lab instrumentation
- Knowledge in system-level timing budget, signal integrity, and power integrity is a plus
- Experience in Verilog, Matlab, Primetime, Nanotime
Salary: The expected base salary ranges for this position are: 196,000 USD – 310,500 USD for Level 5; and 232,000 USD – 368,000 USD for Level 6.
Benefits: You will also be eligible for equity and benefits.