ASIC Physical Design, Sr Engineer in District 7

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years turning RTL into silicon that actually works at 5GHz, not just in simulation, but in the lab when the first testchip comes back. You know that a poorly planned power grid or a clock tree that looked fine in tool reports can kill a tapeout three weeks before the deadline, and you are the kind of engineer who sees those problems during floorplanning, not during signoff.

You are comfortable living in the Synopsys EDA toolchain, moving between Fusion Compiler for place and route, PrimeTime for timing closure, and StarRC for extraction without losing sight of what you are building: a high-speed interface IP that has to meet setup, hold, power, and area targets simultaneously. When a timing path fails by 200ps at a corner you were not expecting, you debug the netlist, check the constraints, talk to the RTL team if needed, and find the fix.

You care about methodology because a good flow means you iterate faster and catch issues earlier. Writing a TCL script that automates floorplan generation is not overhead, it is how you scale. At Synopsys, you will work on interface IP and testchips that go into AI accelerators, autonomous vehicle SoCs, and 5G infrastructure at 7nm, 5nm, and 3nm nodes.

Responsibilities

• Drive complete digital implementation from RTL to GDS for high-speed interface IPs including Serdes, DDR, HDMI, MIPI, and USB at 7nm, 5nm, and 3nm nodes
• Execute synthesis, floorplanning, power planning, clock tree synthesis, placement, routing, and physical verification using Synopsys EDA tools
• Perform static timing analysis and close timing across multiple process corners, voltages, and operating modes
• Run EMIR signoff, analyze IR drop and electromigration, and iterate on power grid design to ensure reliable silicon operation
• Build physical design methodologies and automation scripts using TCL, Python, Perl, and Make to improve efficiency across projects
• Collaborate with RTL designers, verification teams, product engineers, and customers to ensure timely delivery and resolve technical issues
• Provide technical support to customers during IP integration and debug design issues as they arise

The Impact You Will Have

• Enable cutting-edge AI, autonomous vehicle, high-performance compute, cloud, 5G, and IoT applications by delivering silicon-proven interface IP
• Accelerate time to market for Synopsys customers by providing production-ready IP and testchips that integrate cleanly into advanced SoC designs
• Improve physical design quality across the IP portfolio by creating reusable methodologies and automation that scale across projects and process nodes
• Reduce design iteration cycles and signoff risk by catching timing, power, and physical issues early through disciplined analysis
• Strengthen customer confidence by delivering IP that works the first time in silicon and providing responsive technical support
• Contribute to Synopsys leadership in the interface IP market by pushing the boundaries of what is possible at 3nm and beyond

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
• 3+ years of hands-on experience in ASIC physical implementation, specifically RTL to GDS flows using industry-standard EDA tools
• Deep understanding of IC design fundamentals, physical implementation flows, and signoff methodologies for deep submicron designs
• Proficiency with industry-standard data formats including Verilog, GDS, LEF, DEF, SDF, LIB, UPF, CPF, and SPEF
• Strong scripting skills in TCL, Python, Perl, Unix Shell, and Make for automation and flow development
• Solid written and verbal communication skills in English for technical documentation and cross-functional collaboration
• Experience with Synopsys physical design tools such as Fusion Compiler, IC Compiler II, PrimeTime, or StarRC is a strong plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries