Description
Define, design, and develop emulation environments for complex, large-scale networking ASICs.
You will develop state-of-the-art emulation environments to evaluate the performance and functionality of multi-terabit systems.
Key responsibilities:
- Develop emulation infrastructure using C/C++, TCL, Python, etc.
- Develop and test various emulation flows and contribute to different aspects of ASIC verification for bug-free Silicon.
- Collaborate closely with the design team and the hardware team to verify the ASIC in emulation and during ASIC bring-up.
- Work closely with the design, DV, power, and post-silicon diagnostic teams.
- Assist with test plan design, test implementation, and debugging during the pre-silicon emulation process.
- Develop tests to generate complex traffic, performance scenarios to catch potential post-Silicon issues during the Pre-Silicon phase.
Minimum qualifications:
- Bachelor's degree + 8 years of related experience, or Master's degree + 6 years of related experience.
- Design Emulation background with hands-on experience with emulation platforms like Veloce/Palladium/Zebu.
- Fluent in System Verilog or Verilog to work on the Emulation infrastructure development work.
- In-depth knowledge of C/C++, scripting, as well as ASIC design and verification flow.
- Expertise in RTL development for Emulation prototypes.
- System debug experience using tools like gdb, waveform debuggers.
Preferred qualifications:
- Strong hands-on experience with scripting programs (e.g., Python, Perl or similar).
- Strong communication skills and ability to work as a team.
- Post Silicon functional validation or debugging experience is a plus.
- Knowledge of protocols like PCIe, I2C, Ethernet.
- Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.
- Excellent communication skills both verbal and written.