Description
We are seeking a VLSI Design Verification Masters Level Intern to join our team developing HPE Slingshot, an industry-leading interconnect used in some of the world's largest HPC and AI systems. As an intern, you'll work alongside experienced architects, logic designers, and verification engineers on a switch or NIC ASIC verification project for a future generation of Slingshot.
Responsibilities:
- Develop SystemVerilog and UVM testbench components, including models, monitors, scoreboards, and checkers
- Write constrained-random tests
- Develop and analyze functional coverage to identify verification gaps
- Debug regression failures and help identify, log, and resolve logic bugs
- Work directly with ASIC designers and architects
- Use scripting, automation, and AI-assisted tools to improve the verification process
Requirements:
- Pursuing a Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
- Coursework in digital design and computer architecture
- Experience with object-oriented programming
- Strong analytical and problem-solving skills
- Clear written and verbal communication skills
- Willingness to ask questions, explain your reasoning, and participate in technical discussions
Preferred skills:
- Experience with a hardware description language such as Verilog, SystemVerilog, or VHDL
- Experience with Python, Perl, Tcl, or another scripting language
- Experience working in Linux development environments
- Academic, research, or personal projects involving digital hardware
- Experience working as part of a distributed team