Description
We are seeking an ASIC DFT DV Technical Leader to join our team in Yerevan, Armenia. This is a hybrid role with four days per week at Cisco's Yerevan office.
Our team is dedicated to advancing DFT architecture to ensure robust test planning and development that supports ATE screening, in-system testing, debugging, and diagnostics. We collaborate closely with design, design-verification, and product development teams to integrate and validate test logic throughout implementation and post-silicon validation phases.
As a Technical Leader, you will lead the development and execution of comprehensive test benches to verify DFT architectures, ensuring thorough coverage of design specifications. You will collaborate cross-functionally to integrate test logic and validate it across all implementation stages and post-silicon validation flows. You will drive innovation in hardware DFT and test strategies for emerging silicon device models, promoting reusable methodologies and standards.
Minimum qualifications:
- Bachelor's or Master's Degree in Electrical, Computer Engineering or any relevant field.
- 10+ years of experience in design verification or ASIC design.
- Proven experience in test planning based on complex design specifications.
- Proficiency in debugging using DVE/Verdi tools.
- Experience in scripting languages like Tcl, Python, or Perl.
Preferred qualifications:
- Experience in testbench development using SystemVerilog.
- Knowledge of JTAG protocol, scan architecture, MBIST, and boundary scan.
- Familiarity with innovative hardware DFT and test strategy development.
- Ability to lead and mentor engineers.
- Strong problem-solving skills with minimal mentorship.