Field Applications Engineer, Verification

We are seeking a Field Applications Engineer, Verification to join our team at Synopsys. As a Field Applications Engineer, you will work with semiconductor teams across Europe who depend on verification tools to catch issues that would otherwise cost months in silicon.

You have spent years in verification, close enough to the tools to know what breaks and close enough to customers to know the right answer depends on what they are actually trying to verify. You have debugged enough RTL and traced enough CDC violations to understand verification is about building confidence the design will work when it ships.

Your responsibilities will include:

• Supporting pre-sales demos, benchmarks, and proof-of-concept work that helps customers evaluate verification solutions
• Deploying and troubleshooting verification tools post-sale, resolving issues with customer engineering teams
• Applying expertise in static verification using SpyGlass, formal verification with VC Formal, or dynamic simulation using VCS and UVM
• Working with R&D to communicate customer needs and reproduce issues
• Delivering technical workshops and training on verification technologies
• Building trusted relationships with engineering and management at semiconductor companies across Italy and Europe

The impact you will have:

• Enabling customers to catch critical design issues earlier, reducing respins and schedule risk
• Accelerating tool deployment by resolving blockers and providing methodology guidance
• Influencing product roadmaps by surfacing customer requirements
• Helping close deals by running evaluations that demonstrate value on customer designs
• Reducing support escalations by diagnosing issues and providing R&D with context

To be successful in this role, you will need:

• A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
• 5+ years in the semiconductor industry at an EDA company or semiconductor design company
• Hands-on experience in RTL verification or verification methodology
• Strong knowledge in static verification (SpyGlass), formal verification (VC Formal), or dynamic simulation (VCS, UVM)
• Proficiency in Verilog and SystemVerilog
• Comfort with Linux and scripting in Tcl, Python, Perl, or shell
• Fluent English; Italian language skills are a strong advantage