Description
NVIDIA is seeking a Low Power Design/Verification ASIC Engineer to join their team. The successful candidate will work on developing state-of-the-art GPUs to power AI, Automotive, GeForce, and Mobile products.
Job Summary: As a Low Power Design/Verification ASIC Engineer, you will work closely with the Low Power Architecture, Design, and Software teams to understand next-generation features. You will be responsible for architecting, developing testbenches, infrastructure, and test plans to verify various power management solutions for NVIDIA products.
Responsibilities:
- Work closely with Low Power Architecture, Design, and Software teams to understand next-generation features.
- Architect and develop testbenches, infrastructure, and test plans to verify various power management solutions for NVIDIA products.
- Bring creative ideas to improve power-aware DV methodologies and influence EDA vendors to improve simulation and debug efficiencies.
Requirements:
- Recently completed a BS, MS or PhD in Electrical or Computer Engineering, or equivalent experience.
- Understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS).
- Good understanding of processor architecture (GPU is a plus) and related power management design/DV techniques.
- Experience with Incisive Low-Power or Synopsys VCS NLP.
- Strong debug skills and experience with Verdi.
- Fluency in Verilog, SystemVerilog, and understanding of UVM.
Nice to Have:
- Prior knowledge of Low Power Architecture, Low Power CV, and deep learning.
- Good understanding of power intent in UPF format.
- Strong background in Low Power architectures or verification.
- Scripting abilities in Python or PERL.
- Knowledge of C or C++.
Salary: The base salary range is 100,000 USD - 166,750 USD for Level 1, and 116,000 USD - 189,750 USD for Level 2.
Benefits: You will also be eligible for equity and benefits.