Description
We are seeking a visionary and technically rigorous Design Verification Manager to lead our world-class silicon verification team. In this pivotal leadership role, you will architect, guide, and execute advanced verification strategies for high-performance, next-generation semiconductor products.
As a manager, you will bridge the gap between high-level architectural complexity and flawlessly executed silicon. You will be responsible for leading an elite engineering group, driving the adoption of cutting-edge methodology, and ensuring zero-bug tape-outs.
Key Responsibilities
- Team Leadership & Mentorship: Manage, inspire, and grow a team of high-performing design verification engineers. Foster a culture of technical excellence, continuous learning, and collaborative accountability.
- Allocating resources effectively across multiple parallel chip/block schedules.
- Verification Strategy & Architecture: Define global verification strategies, infrastructure, and execution plans for complex SoC and IP blocks. Own the testbench architecture from initial specifications down to structural sign-off.
- Methodology Champion: Drive standard-setting execution using industry-best paradigms, ranging from advanced functional metric tracking to pioneering automated flows. Lead the team across block, sub-system, and full-chip verification environments.
- Cross-Functional Collaboration: Align closely with Architecture, RTL Design, Physical Design, and Post-Silicon validation teams to identify coverage gaps, debug system-level failures, and ensure timely tape-out milestones.
Core Technical Domain Expertise
- Languages & Frameworks: Deep, expert-level fluency in SystemVerilog and Universal Verification Methodology (UVM) architecture.
- Formal Verification: Proven track record of leveraging formal methods to definitively mathematically prove block-level assertions and catch deep corner-case bugs.
- Emulation & Hardware Acceleration: Strategic experience utilizing emulation platforms (e.g., Palladium, Zebu, Veloce) to shift-left software integration and accelerate massive system-level test suites.
Qualifications
- Education: Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a closely related technical field.
- Verification Experience: 10+ years of deep, hands-on industry experience in pre-silicon ASIC/SoC Design Verification.
- Management Experience: 5+ years of dedicated engineering management or formal team leadership experience directly managing engineering headcount, performance reviews, and project delivery schedules.
- Proven mastery of building scalable UVM-compliant testbenches from scratch.
Benefits
- Health & Wellbeing: Comprehensive suite of benefits that supports physical, financial, and emotional wellbeing.
- Personal & Professional Development: Specific programs catered to helping you reach any career goals you have.
- Unconditional Inclusion: Celebrate individual uniqueness and have the flexibility to manage work and personal needs.