Description
We are now looking for a SOC Verification Engineers! NVIDIA is seeking outstanding SOC Verification Engineers to verify world’s leading Smart Network Interface Cards (Smart-NICs) and Data Processing Units (DPUs).
NVIDIA’s Networking Chip Design group works on Smart-NICs and DPUs which help accelerate network performance while reducing the CPU overhead of Internet Protocol (IP) packet transport, freeing more processor cycles to run applications. These networking processors also embed innovative hardware engines that offload and accelerate security with in-line encryption/decryption.
With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA Smart-NICs and DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications!
The Networking Chip Design in India is a new team which is growing at a fast pace! We are currently seeking Verification Engineers with strong verification fundamentals to work in NVIDIA Networking Group's SOC team.
As a SOC Verification Engineer at NVIDIA, be responsible for verification of the design, architecture and micro-architecture with opportunities for pre-silicon, emulation, and post-silicon activities. You will be working closely with architects, designers, emulation team, Software teams, pre and post silicon verification teams to accomplish your tasks.
Responsibilities:
- Be responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.
- Come up with verification infrastructure and automated flows to ease the process of integrating multiple IPs
- Use advanced verification methodologies like e-specman, SV-UVM etc. and have good grasp of scripting languages like python,perl etc.
- Partnering closely with our design team to understand our architecture and the collaborate with Quality Assurance engineers to deliver excellent test coverage and improve the Hardware quality.
- Coordinate with internal and external teams across time zones.
Requirements:
- BS or MS in EEE or ECE with 4+ years of experience in design verification
- Good understanding of Logic Design and Architecture.
- Strong coding skills in SV, scripting languages (Perl/python) and C++.
- Ability to collaborate and work with multiple groups
- Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).
- Exposure to Cluster/Sub-system/Fullchip/SOClevel verification environments
Preferred Qualifications:
- Prior experience of SmartNICs (or DPU) and/or high-speed interconnects.
- Strong debugging, problem-solving and analytical skills.
- Scripting knowledge (Python/Perl/shell).
- Good interpersonal skills and ability & desire to work as an excellent teammate.