Description
We are seeking an expert and skilled Formal Equivalence Checking Methodology Engineer to join our VLSI team. This team is responsible for developing, maintaining, and optimizing RTL verification methodologies - Logical Equivalence and RTL Lint, for our groundbreaking VLSI designs.
As a Formal Equivalence Checking Methodology Engineer, you will develop and maintain robust equivalence checking flows (FEC/FEV) for different stages of the VLSI design cycle, including RTL-to-RTL, RTL-to-Gate, and Gate-to-Gate equivalence checking. You will collaborate with ASIC design teams to understand design requirements and constraints, optimize flows and methodologies for performance, capacity, and debug capabilities, and provide training and support to IP teams on formal verification methodologies, tools, and standard processes.
To succeed in this role, you will need a BS in Electrical, Computer Engineering or equivalent experience with 3+ years of CAD experience; MS preferred. You should be familiar with Verilog and ASIC design along with experience in commercial EDA tools, knowledge or experience with Equivalence checking (FEC or FEV) and RTL Linting flows, strong scripting skills in languages such as Python, or Perl, excellent problem-solving, debugging, and analytical skills, and ability to work in a team environment and collaborate efficiently with multi-functional teams.
Experience in other ASIC methodologies such as RTL Lint or Logic Synthesis, experience with advanced formal verification techniques, such as sequential equivalence checking, X-verification, and low-power equivalence sign-off, and strong understanding of AI and machine learning concepts, frameworks, or applications are highly desirable.