Senior ASIC Verification Engineer - Networking Chip Design

We're looking for a Senior ASIC Engineer to spearhead the delivery of our next-generation Switch Silicon. This is a unique opportunity to move beyond IP-level design and focus on an industry-leading-complex fullchip activities with a strategic leadership required.

As a member of NVIDIA's Networking business unit, you'll join a group of engineers to deliver the next generation state of the art Switch Silicon chips. In this position, you'll show your leadership and make a real impact on a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

Responsibilities:

• Lead a team of engineers to deliver high-performance Switch Fullchip designs (including top level assembly, integrations, DV, etc.). You will ensure strict alignment with chip schedules and maintain NVIDIA’s rigorous quality standards.

• Deep dive into Switch chips’ internals to master the microarchitecture and execution tools/workflows. You will proactively identify workflow bottlenecks and drive continuous improvements to team productivity.

• Partner with leadership across different sites to balance resources, synchronize workflows, and share best practices across the organization.

• Act as a technical mentor for the local team, fostering a culture of team working, efficiency and innovation.

Requirements:

• B.S. or M.S. in Electrical Engineering, Microelectronics, Computer Engineering, or equivalent experience.

• 8+ years of relevant experience in ASIC Design or Verification, with significant experience in a Leader or Management capacity.

• Fluent English (written and oral) is a must. You should be comfortable presenting technical data and project status to global stakeholders.

• A team-first mentality with the interpersonal skills required to lead, motivate, and eventually manage a high-performing engineering group.

• A strong background in Fullchip-level challenges, such as RTL integration, top-level verification, or complex SoC-level verification environment or flow is a big plus.