ASIC Physical Design Engineer

We are seeking an ASIC Physical Design Engineer to join our team. As an ASIC Physical Design Engineer, you will work on physical design from RTL to GSDII, including design quality check, synthesis, formal check, partitioning, constraint creation, async check, timing analysis, and fixing/signoff. You will collaborate with experts in various areas and drive physical-friendly design across multiple teams, including ASIC/P&R/DFT/SI/ARCH. You will work on the most advanced process/technology for the largest chip in the world.

Responsibilities

• Perform STA for hierarchical designs
• Create and validate constraints, and establish timing budgets
• Achieve timing closure at both partition and full-chip levels
• Handle special timing closure tasks, such as IO, test, and clock
• Conduct synthesis and netlist quality checks, as well as formal verification
• Implement chip partitioning and floorplanning
• Create functional ECOs
• Develop and enhance the entire timing closure flow from frontend to backend
• Automate flow development and methodology in relevant areas

Requirements

• Master's degree in Electrical Engineering, Computer Science, or Microelectronics with 1+ year of experience
• Experience with IC design implementation
• Knowledge of circuit design and digital design principles
• Familiarity with EDA software from Synopsys (FC/DC/PT/Formality) and Cadence (RC compiler/Genus/LEC)
• Proficiency in Python, Perl, or TCL
• Excellent English reading and writing skills

Preferred Qualifications

• Proficient user of Perl, Python, or TCL
• Excellent English communication skills