ASIC Digital Verification- Principal Engineer

We are seeking a highly skilled Principal Engineer to lead our ASIC Digital Verification team. As a Principal Engineer, you will be responsible for developing and maintaining high-quality digital verification environments, including UVM, SystemVerilog, and C++.

What you'll do

• Develop and maintain high-quality digital verification environments, including UVM, SystemVerilog, and C++.
• Collaborate with cross-functional teams to develop and verify complex digital designs.
• Identify and prioritize verification tasks to meet project timelines and quality standards.
• Develop and execute verification plans, including testbenches, test cases, and coverage metrics.
• Collaborate with design teams to develop and verify complex digital designs.

What you need

• Bachelor's degree in Computer Science, Electrical Engineering, or related field.
• 10+ years of experience in digital verification, including UVM, SystemVerilog, and C++.
• Strong understanding of digital design principles and verification methodologies.
• Excellent communication and collaboration skills.
• Experience with Agile development methodologies and version control systems.