Lead Performance Modeling Architect, CPU Fabric and LLC

We are seeking a Lead Performance Modeling Engineer to guide our performance architecture team. You will act as the primary architect for performance models covering next-generation cache hierarchies and I/O coherent interconnects. These models will scale from Automotive to Data Center platforms.

As a technical lead, you will balance individual technical contributions with team mentorship and multi-functional strategy.

Responsibilities:

• Define the long-term vision for our modeling infrastructure, choosing between cycle-accurate, analytical, and stochastic modeling approaches to meet project achievements.

• Lead a team of modeling engineers, offering in-depth technical mentorship, conducting code/architecture reviews, and encouraging a culture of rigorous data-driven decision-making.

• Act as the primary liaison between Architecture, RTL Build, and Software teams to resolve complex performance bottlenecks and trade-offs.

• Drive the adoption of advanced modeling methodologies (e.g., hybrid emulation/simulation, AI-based performance optimization) to accelerate the build cycle.

• Allocate simulation workloads and engineering efforts across several simultaneous projects in the automotive and data center sectors.

Requirements:

• A Master’s or Ph.D. in Computer Engineering or a related field (or equivalent experience), with 8+ years of experience in high-performance silicon architecture.

• Extensive experience managing technical teams or complex projects in the field of performance modeling or computer architecture.

• Proficiency in cache coherency protocols (e.g., AMBA CHI, MESI), memory sub-systems, and high-speed interconnect fabric build.

• Significant experience building and architecting large-scale simulators in C++ or SystemC, with a focus on modularity and simulation speed.

• A track record of using statistical analysis to validate model accuracy against RTL or silicon and the ability to explain complex performance 'cliffs' to executive collaborators.

Preferred Qualifications:

• Full-Stack Performance Experience: You have seen the entire lifecycle of an interconnect,from a whiteboard sketch and C++ model to RTL integration and post-silicon performance tuning.

• Standardization Influence: Active participation in industry bodies (e.g., CXL Consortium, Arm ecosystem committees) or a history of published architectural research.

• Scalability Expertise: You have a proven record of addressing the outstanding challenges of both low-latency, safety-critical clusters and massive, high-bandwidth mesh networks for cloud-scale deployments.

• Critical Thinking: The ability to explain not just how a system works, but also how architectural decisions affect the total cost of ownership for data centers or safety margins in automotive.