Description
Join our outstanding Networking Silicon engineering team in developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency. As a Senior Chip Design Verification Engineer, you will be responsible for joining the Tel-Aviv/Beer-Sheva group, working on verification in the field of encryption accelerators. Your daily work will involve verification and might involve any or all aspects of chip development including micro-architecture. You will work closely with firmware and other groups around the globe in a hybrid home-office work mode.
Key responsibilities include: Verification of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area, and performance. Daily work will involve verification and might involve any or all aspects of chip development including micro-architecture. Work closely with firmware and other groups around the globe.
Requirements include: B.SC./M.SC. or equivalent experience in Electrical Engineering/Communication Engineering/Computer Engineering. 5+ years of validated experience in RTL Frontend ASIC verification (Chip Design). High Level of English. Highly motivated and a team player.
Nice to have skills include: Knowledge in Specman. Knowledge and experience in the encryption field. Experience in RTL Frontend ASIC Design. Knowledge in Verilog.