Chip Power Estimation Engineer

NVIDIA is seeking a Chip Power Estimation Engineer to work on architectural power estimation for GPUs and SOCs. The successful candidate will develop advanced power models to estimate chip and board power under product-driven use cases.

The role involves understanding high-level chip architecture, application use-cases, low power design techniques, and process technology aspects that impact dynamic and leakage power. The engineer will develop the estimation infrastructure, estimate power consumption under various scenarios, and collaborate with architecture, design, synthesis, timing, circuit, and post-silicon teams.

Key responsibilities:

• Develop and correlate power estimation models and tools for NVIDIA's chips
• Architect and develop power models for use-cases, idle power, and IO power
• Design tools based on these models and their testing methodology and infrastructure
• Correlate and calibrate power models using measured silicon data
• Analyze and decide on chip configuration and process technology options to optimize power/performance for NVIDIA's upcoming chips
• Study and contribute to performance/watt improvement ideas for NVIDIA's GPUs and SOCs

Requirements:

• B.Tech./M.Tech with 2+ years of experience in power/performance estimation and optimization techniques
• Strong fundamentals in power, including transistor-level leakage and dynamic characteristics of VLSI circuits
• Familiarity with low power design techniques such as multi VT, clock gating, power gating, and dynamic voltage-frequency scaling (DVFS)
• Strong background in power estimation techniques, flows, and algorithms
• Good programming skills, preferably Python, and object-oriented programming and design

Preferred qualifications:

• Exposure to lab setup, including power measurement equipment such as scope/DAQ, and ability to analyze board-level power issues
• Experience with power analysis EDA tools such as PTPX/EPS
• Good communication skills and desire to work as a great teammate