Analog Design, Sr Staff Engineer

At Synopsys, you will work on designing and developing cutting-edge semiconductor solutions as an Analog Design, Sr Staff Engineer. You will focus on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP, working with a cross-functional design team.

Your responsibilities will include:

• Designing and proposing advanced algorithms to calibrate and adapt transceivers for optimal performance.
• Identifying and refining circuit implementations to achieve optimal power, area, and performance targets.
• Developing and maintaining SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Owning Analog Macro level design and reviewing SerDes standards and architecture documents to develop analog specifications.
• Overseeing physical layout to minimize the effect of parasitics, device stress, and process variation.
• Correlating simulated performance with silicon measurements to ensure accuracy and reliability.
• Collaborating with cross-functional teams throughout all stages of development and post-silicon.
• Contributing to lab testing and analysis for high-speed serial links.

Requirements:

• M.Sc. or Ph.D. in Electrical or Computer Engineering with 6+ years of SerDes/High-Speed analog design experience.
• Silicon-proven experience implementing circuits for the TX, RX, and Clock paths within a SerDes.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for PAM4 high-speed serial links.
• Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Detailed design experience with several of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC.
• Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance.

Benefits:

• Comprehensive medical and healthcare plans.
• Time away programs, including ETO and FTO.
• Family support, including maternity and paternity leave.
• ESPP program.
• Retirement plans.
• Competitive salaries.

The ideal candidate is an accomplished analog design engineer with a passion for pushing the boundaries of high-speed connectivity, and a proven track record of successfully taping out silicon-proven designs.