Description
We are looking for a Senior Mask Layout Design Engineer to join our growing team of diverse individuals responsible for handling meaningful high-speed mixed-signal circuit designs. As a Senior Mask Layout Design Engineer, you will be performing physical layout for mixed-signal functions like PLLs, high-speed SerDes, Analog to Digital converters, and ESD structures designs in groundbreaking sub-micron CMOS technologies using Cadence tools.
You will work cross-functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. You will also take part in floor planning, custom layout, and verifying against design rules and schematics.
The ideal candidate will have a BSEE or equivalent experience, minimum of 5+ years proven experience in Mask and Layout Design, deep understanding of analog circuit layout concepts in submicron CMOS technologies, and expertise in Cadence custom circuit design tools, particularly Virtuoso. Additionally, you should have experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield.
As a team player, you will be able to work optimally in a team, possess good interpersonal skills, and have a passion for positive energy. Proficiency in scripting languages like Perl, Python, and Skill is also required. Furthermore, you should have knowledge of DRC and LVS checking flows and the ability to customize decks.